View DAC8512FS_1394246.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a +5 v, serial input complete 12-bit dac dac8512 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 functional block diagram 7 8 1 2 3 4 5 6 ref 12-bit dac dac register v dd v out gnd serial register 12 12 clr ld cs clk sdi features space saving so-8 or mini-dip packages complete, voltage output with internal reference 1 mv/bit with 4.095 v full scale single +5 volt operation no external components 3-wire serial data interface, 20 mhz data loading rate low power: 2.5 mw applications portable instrumentation digitally controlled calibration servo controls process control equipment pc peripherals general description the dac8512 is a complete serial input, 12-bit, voltage output digital-to-analog converter designed to operate from a single +5 v supply. it contains the dac, input shift register and latches, reference and a rail-to-rail output amplifier. built using a cbcmos process, these monolithic dacs offer the user low cost, and ease of use in +5 v only systems. coding for the dac8512 is natural binary with the msb loaded first. the output op amp can swing to either rail and is set to a range of 0 v to +4.095 vfor a one-millivolt-per-bit resolution. it is capable of sinking and sourcing 5 ma. an on-chip reference is laser trimmed to provide an accurate full-scale output voltage of 4.095 v. serial interface is high speed, three-wire, dsp compatible with data in (sdi), clock (clk) and load strobe (ld). there is also a chip-select pin for connecting multiple dacs. a clr input sets the output to zero scale at power on or upon user demand. the dac8512 is specified over the extended industrial (C40 c to +85 c) temperature range. dac8512s are available in plas- tic dips and so-8 surface mount packages. 1.0 ?.0 4096 ?.5 ?.75 0 0 ?.25 0.25 0.5 0.75 3072 2048 1024 digital input code ?decimal linearity error ?lsb linearity error vs. digital input code
rev. a C2C dac8512Cspecifications electrical characteristics parameter symbol condition min typ max units static performance resolution n note 2 12 bits relative accuracy inl e grade C1 1/4 +1 lsb f grade C2 3/4 +2 lsb differential nonlinearity dnl no missing codes C1 3/4 +1 lsb zero-scale error v zse data = 000 h +1/2 +3 lsb full-scale voltage v fs data = fff h 3 e grade 4.087 4.095 4.103 v f grade 4.079 4.095 4.111 v full-scale tempco tcv fs notes 3, 4 16 ppm/ c analog output output current i out data = 800 h 5 7ma load regulation at full scale l reg r l = 402 w to , data = 800 h 1 3 lsb capacitive load c l no oscillation 4 500 pf logic inputs logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 10 m a input capacitance c il 10 pf interface timing specifications 1, 4 clock width high t ch 30 10 ns clock width low t cl 30 10 ns load pulse width t ldw 20 ns data setup t ds 15 10 ns data hold t dh 15 5 ns clear pulse width t clrw 30 20 ns load setup t ld1 15 ns load hold t ld2 10 ns select t css 30 ns deselect t csh 20 ns ac characteristics 4 voltage output settling time t s to 1 lsb of final value 5 16 m s dac glitch 15 nv s digital feedthrough 15 nv s supply characteristics positive supply current i dd v ih = 2.4 v, v il = 0.8 v, no load 1.5 2.5 ma v dd = 5 v, v il = 0 v, no load 0.5 1 ma power dissipation p diss v ih = 2.4 v, v il = 0.8 v, no load 7.5 12.5 mw v dd = 5 v, v il = 0 v, no load 2.5 5 mw power supply sensitivity pss d v dd = 5% 0.002 0.004 %/% notes 1 all input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 v) and timed from a voltage level of 1.6 v. 2 1 lsb = 1 mv for 0 v to +4.095 v output range. 3 includes internal voltage reference error. 4 these parameters are guaranteed by design and not subject to production testing. 5 the settling time specification does not apply for negative going transitions within the last 6 lsbs of ground. some devices exhibit double the typical settling time in this 6 lsb region. specifications subject to change without notice. (@ v dd = +5.0 v 6 5%, C40 8 c t a +85 8 c, unless otherwise noted)
rev. a C3C dac8512 wafer test limits (@ v dd = +5.0 v 6 5%, t a = +25 8 c, applies to part number dac8512gbc only, unless otherwise noted) parameter symbol condition min typ max units static performance relative accuracy inl C2 3/4 +2 lsb differential nonlinearity dnl no missing codes C1 0.7 +1 lsb zero-scale error v zse data = 000 h +1/2 +3 lsb full-scale voltage v fs data = fff h 4.085 4.095 4.105 v logic inputs logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 10 m a supply characteristics positive supply current i dd v ih = 2.4 v, v il = 0.8 v, no load 1.5 2.5 ma v dd = 5 v, v il = 0 v, no load 0.5 1 ma power dissipation p diss v ih = 2.4 v, v il = 0.8 v, no load 7.5 12.5 mw v dd = 5 v, v il = 0 v, no load 2.5 5 mw power supply sensitivity pss d v dd = 5% 0.002 0.004 %/% note electrical tests are performed at wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. absolute maximum ratings* v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +10 v logic inputs to gnd . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v out to gnd . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v i out short circuit to gnd . . . . . . . . . . . . . . . . . . . . . . 50 ma package power dissipation . . . . . . . . . . . . . . (t j max C t a )/ q ja thermal resistance q ja 8-pin plastic dip package (p) . . . . . . . . . . . . . . . . 103 c/w 8-lead soic package (s) . . . . . . . . . . . . . . . . . . . 158 c/w maximum junction temperature (t j max) . . . . . . . . . +150 c operating temperature range . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the dac8512 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide inl temperature package package model (lsb) range description option dac8512ep 1 C40 c to +85 c 8-pin p-dip n-8 dac8512fp 2 C40 c to +85 c 8-pin p-dip n-8 DAC8512FS 2 C40 c to +85 c 8-lead soic so-8 dac8512gbc 2 +25 c dice
dac8512 C4C rev. a clr t csh d11 d10 d9 d8 d7 d6 d5 d3 d4 d1 d2 d0 t ld2 t css t ld1 t s t dh t ds t cl t ch t ldw t s t clrw 1 lsb error band sdi clk cs sdi clk fs zs v out ld ld figure 1. timing diagram data shift register esd protection diodes to v dd and gnd sdi cs clk figure 2. equivalent clock input logic table i. control-logic truth table cs 2 clk 2 clr ld serial shift register function dac register function h x h h no effect latched l l h h no effect latched l h h h no effect latched l - + h h shift-register-data advanced one bit latched - + l h h shift-register-data advanced one bit latched hx h C no effect updated with current shift register contents h x h l no effect transparent h x l x no effect loaded with all zeros hx - + h no effect latched all zeros notes l - + positive logic transition; C negative logic transition; x = dont care. 2 cs and clk are interchangeable. 3 returning cs high avoids an additional false clock of serial data input. 4 do not clock in serial data while ld is low.
dac8512 C5C rev. a pin configurations so-8 p-dip-8 & cerdip-8 1 2 3 4 8 7 6 5 top view (not to scale) dac8512 1 2 3 4 8 7 6 5 top view (not to scale) dac8512 v out gnd clr ld v dd clk sdi cs v out gnd clr ld v dd clk sdi cs pin descriptions pin name description 1v dd positive supply. nominal value +5 v, 5%. 2 cs chip select. active low input. 3 clk clock input for the internal serial input shift register. 4 sdi serial data input. data on this pin is clocked into the internal serial register on positive clock edges of the clk pin. the most significant bit (msb) is loaded first. 5 ld active low input which writes the serial register data into the dac register. asynchronous input. 6 clr active low digital input that clears the dac register to zero, setting the dac to minimum scale. asynchronous input. 7 gnd analog ground for the dac. this also serves as the digital logic ground reference voltage. 8v out voltage output from the dac. fixed output voltage range of 0 v to 4.095 v with 1 mv/lsb. an internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature and power supply variations. dice characteristics substrate is common with v dd . number of transistors : 642 die size: 0.055 inch 0.106 inch; 5830 sq mils 1 2 3 4 5 6 7 7 8 v dd cs clk sdi ld clr gnd gnd v out operation the dac 8512 is a complete ready to use 12-bit digital-to-analog converter. it contains a voltage-switched, 12-bit, laser-trimmed dac, a curvature-corrected bandgap reference, a rail-to-rail output op amp, a dac register, and a serial data input register. the serial data interface consists of a clk, serial data in (sdi), and a load strobe ( ld ). this basic 3-wire interface offers maxi- mum flexibility for interface to the widest variety of serial data input loading requirements. in addition a cs select is provided for multiple packaging loading and a power on reset clr pin to simplify start or periodic resets. d/a converter section the dac is a 12-bit voltage mode device with an output that swings from gnd potential to the 2.5 volt internal bandgap voltage. it uses a laser trimmed r-2r ladder which is switched by n channel mosfets. the output voltage of the dac has a constant resistance independent of digital input code. the dac output is internally connected to the rail-to-rail output op amp. amplifier section the dacs output is buffered by a low power consumption pre- cision amplifier. this amplifier contains a differential pnp pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zero-scale dac output volt- ages. the rail-to-rail amplifier is configured in a gain of 1.6384 (= 4.095 v/2.5 v) in order to set the 4.095 volt full-scale output (1 mv/lsb). see figure 3 for an equivalent circuit schematic of the analog section. r1 r2 v out rail-to-rail output amplifier r bandgap reference 2r r 2r 2r 2r spdt n-ch fet switches 2r av = 4.095/2.5 = 1.638v/v voltage switched 12-bit r-2r d/a converter buffer 2.5v figure 3. equivalent dac8512 schematic of analog portion the op amp has a 16 m s typical settling time to 0.01%. there are slight differences in settling time for negative slowing signals vs. positive. see the oscilloscope photos in the typical perfor- mances section of this data sheet.
dac8512 C6C rev. a output section the rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. v dd v out agnd n-ch p-ch figure 4. equivalent analog output circuit figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its n channel pull down fets that will pull an output load directly to gnd. the output sourcing current is provided by a p channel pull up device that can supply gnd terminated loads, especially at the low supply tolerance values of 4.75 volts. figures 5 and 6 provide information on output swing performance near ground and full-scale as a function of load. in addition to resistive load driving capability the amplifier has also been carefully designed and characterized for up to 500 pf ca- pacitive load driving capability. power supply the very low power consumption of the dac8512 is a direct result of a circuit design optimizing use of the cbcmos pro- cess. by using the low power characteristics of the cmos for the logic, and the low noise, tight matching of the complemen- tary bipolar transistors good analog accuracy is achieved. for power consumption sensitive applications it is important to note that the internal power consumption of the dac8512 is strongly dependent on the actual logic input voltage levels present on the sdi, cs , ld , and clr pins. since these inputs are standard cmos logic structures they contribute static power dissipation dependent on the actual driving logic v oh and v ol voltage levels. the graph in figure 9 shows the effect on to- tal dac8512 supply current as a function of the actual value of input logic voltage. consequently use of cmos logic vs. ttl minimizes power dissipation in the static state. a v il = 0 v on the sdi, cs and clr pins provides the lowest standby power dissipation of 2.5 mw (500 m a 5 v). as with any analog system, it is recommended that the dac8512 power supply be bypassed on the same pc card that contains the chip. figure 10 shows the power supply rejection versus frequen- cy performance. this should be taken into account when using higher frequency switched mode power supplies with ripple fre- quencies of 100 khz and higher. one advantage of the rail-to-rail output amplifier used in the dac8512 is the wide range of usable supply voltage. the part is fully specified and tested over temperature for operation from +4.75 v to +5.25 v. if reduced linearity and source current ca- pability near full scale can be tolerated, operation of the dac8512 is possible down to +4.3 volts. the minimum operating supply voltage versus load current plot, in figure 11, provides informa- tion for operation below v dd = +4.75 v. timing and control the dac8512 has a separate serial input register from the 12-bit dac register that allows preloading of a new data value into the serial register without disturbing the present dac out- put voltage. after the new value is fully loaded in the serial in- put register it can be asynchronously transferred to the dac register by strobing the ld pin. the dac register uses a level sensitive ld strobe that should be returned high before any new data is loaded into the serial input register. at any time the contents of the dac register can be reset to zero by strobing the clr pin which causes the dac output voltage to go to zero volts. all of the timing requirements are detailed in figure 1 along with the table i control-logic truth table.
rev. a C7C typical performance characteristics dac8512 5 2 0 10 100 100k 10k 1k 1 3 4 load resistance ? v output voltage ?volts rl tied to agnd d = fffh r l tied to agnd data = fff h v dd = +5v t a = +25 8 c r l tied to +5v data = 000h figure 5. output swing vs. load time = 2ms/div output noise voltage ?500 m v/div 10 90 100 0% scale = 100x code = fff h = 4095 10 bw = 630khz t a = +25 8 c 2ms 50mv figure 8. broadband noise 0.01 0.1 10 1.0 5.0 4.8 4.0 4.6 4.4 4.2 0.04 0.4 4.0 output load current ?ma v dd min ?volts d vfs 1 lsb data = fff h t a = +25 8 c proper operation when v dd supply voltage above curve figure 11. minimum supply voltage vs. load 1 10 1000 100 100 1 0.01 0.1 10 output sink current ? m a output pull-down voltage ?mv v dd = +5v data = 000 h t a = +85 8 c t a = ?0 8 c t a = +25 8 c figure 6. pull-down voltage vs. out- put sink current capability 4.0 0.0 5 0.8 0 2.4 1.6 3.2 3 24 1 logic voltage value ?volts supply current ?ma v dd = +5v t a = +25 8 c no load figure 9. supply current vs. logic input voltage 2.028 2.018 2.048 2.038 0 5 time ?200ns/div v out ?volts ld 2048 10 to 2047 10 v dd = 5v t a = +25 8 c figure 12. midscale dac glitch performance 80 ?00 ?0 ?0 1 ?0 ?0 0 20 40 60 3 2 output voltage ?volts output current ?ma pos 0 current 0 limit 0 neg current limit data = 800 h r l tied to +2v figure 7. short circuit current 100 0 10 100 100k 10k 1k 60 80 20 40 power supply rejection ?db frequency ?hz v dd = +5v 6 200mv ac t a = +25 8 c data = fff h figure 10. power supply rejection vs. frequency 10 90 100 0% time = 20 m s/div 20 m s 1v r l = no load c l = 110pf t a = +25 8 c 1v/div figure 13. large signal settling time
dac8512 typical performance characteristics rev. a C8C 0 5 v dd = +5v t a = +25 8 c r l = no load output voltage 1mv/div time ?10 m s/div ld figure 15. fall time detail 4.115 4.075 125 4.085 4.080 ?5 ?0 4.095 4.090 4.100 4.105 4.110 100 75 50 25 0 temperature ? 8 c full-scale output ?volts v dd = +5v no load ss = 300 pcs avg ?3 s avg + 3 s avg figure 18. full-scale voltage vs. temperature 5 ? 1200 ? ? 200 ? 0 1 ? 0 2 3 4 1000 600 800 400 output voltage change ?mv hours of operation at +125 8 c 135 units tested readings normalized to zero hour time point average range figure 21. long term drift acceler- ated by burn-in 0 5 16 m s v dd = +5v t a = +25 8 c r l = no load output voltage 1mv/div time ?10 m s/div ld figure 14. rise time detail 60 0 total unadjusted error ?mv number of units 0 10 ?2 30 20 40 50 +12 +4 0 ? ? +8 tue = ? inl + zs + fs ss = 300 units t a = +25 8 c figure 17. total unadjusted error histogram 10 0.1 0.01 10 100 100k 10k 1k 1 frequency ?hz v dd = +5v t a = +25 8 c data = fff h output noise density ? m v/ ? hz figure 20. output voltage noise vs. frequency 2.0 ?.0 4096 ?.0 ?.5 512 0 0.0 ?.5 0.5 1.0 1.5 3584 3072 2560 2048 1536 1024 digital input code ?decimal linearity error ?lsb v dd = +5v t a = ?0 8 c, +25 8 c, +85 8 c +25 8 c & +85 8 c ?0 8 c figure 16. linearity error vs. digital code 3 ? 125 0 ?5 ?0 1 2 100 75 50 25 0 temperature ? 8 c zero-scale ?mv data = 000 h no load v dd = +5.0v figure 19. zero-scale voltage vs. temperature 4 0 125 1 ?5 ?0 2 3 100 75 50 25 0 temperature ? 8 c supply current ?ma v logic = 2.4v data = fff h no load v dd = +4.75v v dd = +5.25v v dd = +5.0v figure 22. supply current vs. temperature
dac8512 C9C rev. a applications section power supplies, bypassing, and grounding all precision converter products require careful application of good grounding practices to maintain full rated performance. because the dac8512 has been designed for +5 v applications, it is ideal for those applications under microprocessor or micro- computer control. in these applications, digital noise is preva- lent; therefore, special care must be taken to assure that its inherent precision is maintained. this means that particularly good engineering judgment should be exercised when address- ing the power supply, grounding, and bypassing issues using the dac8512. the power supply used for the dac8512 should be well filtered and regulated. the device has been completely characterized for a +5 v supply with a tolerance of 5%. since a +5 v logic sup- ply is almost universally available, it is not recommended to connect the dac directly to an unfiltered logic supply without careful filtering. because it is convenient, a designer might be inclined to tap a logic circuits supply for the dacs supply. unfortunately, this is not wise because fast logic with nanosec- ond transition edges induce high current pulses. the high tran- sient current pulses can generate glitches hundreds of millivolts in amplitude due to wiring resistances and inductances. this high frequency noise will corrupt the analog circuits internal to the dac and cause errors. even though their spike noise is lower in amplitude, directly tapping the output of a +5 v system supply can cause errors because these supplies are of the switch- ing regulator type that can and do generate a great deal of high frequency noise. therefore, the dac and any associated analog circuitry should be powered directly from the system power sup- ply outputs using appropriate filtering. figure 23 illustrates how a clean, analog-grade supply can be generated from a +5 v logic supply using a differential lc filter with separate power supply and return lines. with the values shown, this filter can easily handle 100 ma of load current without saturating the ferrite cores. higher current capacity can be achieved with larger ferrite cores. for lowest noise, all electrolytic capacitors should be low esr (equivalent series resistance) type. 100 m f elect . 10-22 m f tant. 0.1 m f cer. ttl/cmos logic circuits +5v power supply +5v +5v return ferrite beads: 2 turns, fair-rite #2677006301 figure 23. properly filtering a +5 v logic supply can yield a high quality analog supply in order to fit the dac8512 in an 8-pin package, it was neces- sary to use only one ground connection to the device. the ground connection of the dac serves as the return path for supply currents as well as the reference point for the digital in- put thresholds. the ground connection also serves as the supply rail for the internal voltage reference and the output amplifier. therefore, to minimize any errors, it is recommended that the ground connection of the dac8512 be connected to a high quality analog ground, such as the one described above. gener- ous bypassing of the dacs supply goes a long way in reducing supply line-induced errors. local supply bypassing consisting of a 10 m f tantalum electrolytic in parallel with a 0.1 m f ceramic is recommended. the decoupling capacitors should be connected between the dacs supply pin (pin 1) and the analog ground (pin 7). figure 24 shows how the ground and bypass connec- tions should be made to the dac8512. 6 2 gnd v dd 8 dac8512 10 m f 0.1 m f v out 1 +5v to analog ground cs clr 5 3 4 ld sclk sdi v out 7 figure 24. recommended grounding and bypassing scheme for the dac8512 unipolar output operation this is the basic mode of operation for the dac8512. as shown in figure 24, the dac8512 has been designed to drive loads as low as 2 k w in parallel with 500 pf. the code table for this op- eration is shown in table ii. 10 m f 0.1 m f 0v v out 4.095v +5v 2k w 500pf 6 2 v dd 8 dac8512 1 cs clr 5 3 4 ld sclk sdi 7 gnd v out figure 25. unipolar output operation table ii. unipolar code table hexadecimal number decimal number analog output in dac register in dac register voltage (v) fff 4095 +4.095 801 2049 +2.049 800 2048 +2.048 7ff 2047 +2.047 000 0 0 typical performance characteristics
dac8512 C10C rev. a operating the dac8512 on +12 v or +15 v supplies only although the dac8512 has been specified to operate on a single, +5 v supply, a single +5 v supply may not be available in many applications. since the dac8512 consumes no more than 2.5 ma, maximum, then an integrated voltage reference, such as the ref02, can be used as the dac8512 +5 v supply. the configuration of the circuit is shown in figure 26. notice that the references output voltage requires no trimming because of the ref02s excellent load regulation and tight initial output voltage tolerance. although the maximum supply current of the dac8512 is 2.5 ma, local bypassing of the ref02s output with at least 0.1 m f at the dacs voltage supply pin is recom- mended to prevent the dacs internal digital circuits from af- fecting the dacs internal voltage reference. +12v or +15v 0.1 m f 4 ref02 6 2 0.1 m f 6 2 8 dac8512 v out 1 5 3 4 7 gnd cs clr ld sclk sdi v dd figure 26. operating the dac8512 on +12 v or +15 v supplies using a ref02 voltage reference measuring offset error one of the most commonly specified endpoint errors associated with real world nonideal dacs is offset error. in most dac testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 volt. there are some dacs where offset errors may be present but not observable at the zero scale because of other circuit limi- tations (for example, zero coinciding with single-supply ground). in these dacs, nonzero output at zero code cannot be read as the offset error. in the dac8512, for example, the zero-scale error is specified to be 3 lsbs. since zero scale coincides with zero volt, it is not possible to measure negative offset error. v out 0.1 m f 200 m a, max v 6 2 8 dac8512 1 +5v cs clr 5 3 4 ld sclk sdi r 7 set code = 000 h and measure v out gnd v dd figure 27. measuring zero-scale or offset error by adding a pull-down resistor from the output of the dac8412 to a negative supply as shown in figure 27, offset errors can now be read at zero code. this configuration forces the output p-channel mosfet to source current to the negative supply thereby allowing the designer to determine in which direction the offset error appears. the value of the resistor should be such that, at zero code, current through the resistor is 200 m a, maximum. bipolar output operation although the dac8512 has been designed for single-supply op- eration, bipolar operation is achievable using the circuit illus- trated in figure 28. the circuit uses a single-supply, rail-to-rail op295 op amp and the ref03 to generate the C2.5 v reference required to level-shift the dac output voltage. note that the C 2.5 v reference was generated without the use of precision resis- tors. the circuit has been configured to provide an output voltage in the range C5 v v out +5 v and is coded in com- plementary offset binary. although each dac lsb corresponds to 1 mv, each output lsb has been scaled to 2.44 mv. table iii provides the relationship between the digital codes and out- put voltage. the transfer function of the circuit is given by: v o = C1 mv digital code r 4 r 1 + 2.5 r 4 r 2 and, for the circuit values shown, becomes: v o = C2.44 mv digital code + 5 v +5v 10 m f + 0.1 m f 1 8 7 4 3 2 5 6 dac8512 v dd gnd r1 10k w r2 12.7k r3 247k w 6 5 4 8 7 ?v v o +5v +5v ?v a2 p2 10k w zero scale adjust p3 500 w r4 23.7k w full scale adjust ?.5v clr ld cs sclk sdi 0.1 m f +5v ref03 a1 ?.5v 0.01 m f 100 w p1 10k w 2.5v trim 2 6 5 4 2 1 3 a1, a2 = 1/2 op295 figure 28. bipolar output operation
dac8512 C11C rev. a table iii. bipolar code table hexadecimal number decimal number analog output in dac register in dac register voltage (v) f ff 4095 C4.9976 801 2049 C2.44eC3 800 2048 0 7ff 2047 +2.44eC3 000 0 +5 to maintain monotonicity and accuracy, r1, r2, and r4 should be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient matching. mismatching between r1 and r2 causes offset and gain errors while an r4 to r1 and r2 mismatch yields gain errors. for applications that do not require high accuracy, the circuit illustrated in figure 29 can also be used to generate a bipolar output voltage. in this circuit, only one op amp is used and no potentiometers are used for offset and gain trim. the output voltage is coded in offset binary and is given by: v o = 1 mv digital code r 4 r 3 + r 4 ? ? ? ? 1 + r 2 r 1 ? ? ? ? C2.5 r 2 r 1 43.2k + 499 r1 10k 10k 6 2.5v 6 5v v out range r2 10k 20k r3 10k 10k r4 15.4k + 274 4 6 1 8 4 2 3 3 5 2 4 6 7 8 1 2 cs clr ld sclk sdi v dd gnd dac8512 +5v 0.1? +2.5v r1 r2 ref03 +5v ?v a1 = 1/2 op295 r3 r4 v o +5v 0.1? a1 figure 29. bipolar output operation without trim for the 2.5 v output range and the circuit values shown in the table, the transfer equation becomes: v o = 1.22 mv digital code C 2.5 v similarly, for the 5 v output range, the transfer equation becomes: v o = 2.44 mv digital code C 5 v generating a negative supply voltage some applications may require bipolar output configuration but only have a single power supply rail available. this is very com- mon in data acquisition systems using microprocessor-based systems. in these systems, +12 v, +15 v, and/or +5 v are only available. shown in figure 30 is a method of generating a nega- tive supply voltage using one cd4049, a cmos hex inverter, operating on +12 v or +15 v. the circuit is essentially a charge pump where two of the six are used as an oscillator. for the val- ues shown, the frequency of oscillation is approximately 3.5 khz and is fairly insensitive to supply voltage because r1 > 2 r2. the remaining four inverters are wired in parallel for higher out- put current. the square wave output is level translated by c2 to a negative-going signal, rectified using a pair of 1n4001s, and then filtered by c3. with the values shown, the charge pump will provide an output voltage of C5 v for current loadings in the range 0.5 ma i out 10 ma with a +15 v supply and 0.5 ma i out 7 ma with a +12 v supply. 910 6 11 12 14 15 7 3254 r2 5.1k w r1 510k w c1 0.02 m f c2 47 m f d1 1n4001 c3 47 m f 1n5231 5.1v zener d2 1n4001 r3 470 w ?v inverters = cd4049 figure 30. generating a C5 v supply when only +12 v or +15 v is available a high-compliance, digitally controlled precision current source the circuit in figure 31 shows the dac8512 controlling a high-compliance precision current source using an amp05 in- strumentation amplifier. the amp05s reference pin becomes the input, and the old inputs now monitor the voltage across a precision current sense resistor, r cs . voltage gain is set to unity, so the transfer function is given by the following equation: i out = v in r cs if r cs equals 100 w , the output current is limited to +10 ma with a 1 v input. therefore, each dac lsb corresponds to 2.4 m a. if a bipolar output current is required, then the circuit in figure 28 can be modified to drive the amp05s reference pin with a 1 v input signal. potentiometer p1 trims the output current to zero with the in- put at 0 v. fine gain adjustment can be accomplished by adjust- ing r1 or r2.
dac8512 C12C rev. a 9 18 1 2 17 r1 100k 7 6 r2 5k w p1 100k w 5 4 11 0.1 m f ?5v amp05 10 r cs 100 w 0ma i out 10ma 2.4 m a/ bit 12 0.1 m f +15v +15v 0.1 m f 4 ref02 6 2 0.1 m f r3 3k r4 1k 8 6 2 8 dac8512fz 1 cs clr 5 3 4 ld sclk sdi 7 figure 31. a high-compliance, digitally controlled precision current source a single-supply, programmable current source the circuit in figure 32 shows how the dac8512 can be used with an op295 single-supply, rail-to-rail output op amp to pro- vide a digitally programmable current sink from v source that consumes less than 3.8 ma, maximum. the dacs output volt- age is applied across r1 by placing the 2n2222 transistor in the op295s feedback loop. for the circuit values shown, the full- scale output current is 1 ma which is given by the following equation: i out = dw 4.095 v r 1 where dw = dac8512s binary digital input code. full-scale adjust a1 = 1/2 op295 +5v 6 2 8 dac8512fp 1 cs clr 5 3 4 ld sclk sdi 7 3 2 a1 1 +5v 0.1 m f v s load 2n2222 r1 4.02k w p1 200 w figure 32. a single-supply, programmable current source the usable output voltage range of the current sink is +5 v to +60 v. the low limit of the range is controlled by transistor saturation, and the high limit is controlled by the collector-base breakdown voltage of the 2n2222. a digitally programmable window detector a digitally programmable, upper/lower limit detector using two dac8512s is shown in figure 33. the required upper and lower limits for the test are loaded into each dac individually by controlling hdac/ ldac . if a signal at the test input is not within the programmed limits, the output will indicate a logic zero which will turn the red led on. 2 1 1/6 74hc05 hdac/ldac clr +5v 1k w c1 c2 +5v 12 3 2 1 4 6 7 5 +5v r1 604 w red led t1 34 +5v r2 604 w green led t1 pass/fail c1, c2 = 1/4 cmp-404 1/6 74hc05 v in ld sclk sdi 0.1 m f +5v 2 6 8 dac8512 1 5 3 4 7 0.1 m f +5v 2 6 8 dac8512 1 5 3 4 7 0.1 m f figure 33. a digitally programmable window detector
dac8512 C13C rev. a opto-isolated interfaces for process control environments in many process control type applications, it is necessary to pro- vide an isolation barrier between the controller and the unit be- ing controlled. opto-isolators can provide isolation in excess of 3 kv. the serial loading structure of the dac8512 makes it ideal for opto-isolated interfaces as the number of interface lines is kept to a minimum. illustrated in figure 34 is an opto-isolated interface using the dac8512. in this circuit, the cs line is always low to enable the dac, and the 10 k w /1 m f combination connected to the dacs clr pin sets a turn-on time constant of 10 ms to reset the dac upon application of power. three opto-couplers are then used for the sdi, sclk, and ld lines. often times reducing the number of interface lines to two lines is required in many control environments. the circuit illustrated in figure 35 shows how to convert a two-line interface into the three control lines required to control the dac8512 without us- ing one shots. this technique uses a counter to keep track of the clock cycles and, when all the data has been input to the dac, the external logic generates the ld pulse. 0.1 m f +5v 5 6 8 dac8512 1 cs 3 4 7 2 0.1 m f 10k w +5v v out +5v +5v +5v 10k w sclk 10k w sdi 10k w ld ld sclk sdi +5v reg +5v power high voltage isolation figure 34. an opto-isolated dac interface +5v +5v 10k w 10k w sclk sdi +5v reg +5v power high voltage isolation 74hc161 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 clr clk a b c d enp gnd v cc rco q a q b q c q d ent load +5v 10k w nc nc nc 0.1 m f +5v +5v 10k w x 1 2 3 y 4 5 6 1/4 74hcoo 1/4 74hcoo v dd 0.1 m f 3 5 8 dac8512 1 +5v 4 ld sclk sdi 7 6 clr gnd v out cs 2 +5v 10k w 1 m f figure 35. a two-wire, opto-lsolated dac interface
dac8512 C14C rev. a counter clk q d q c q b q a load (x) dac8512 clk (y) dac8512 clk = load sclk load = q c ? q d load dac figure 36. opto-lsolated two-wire serial interface timing diagram the timing diagram of figure 36 can be used to understand the operation of the circuit. only two opto-couplers are used in the circuit; one for sclk and one for sdi. the 74hc161 counter in incremented on every rising edge of the clock. additionally, the data is loaded into the dac8512 on the falling edge of the clock by inverting the serial clock using gate y. the timing diagram shows that after the twelfth bit has been clocked the output of the counter is binary 1011. on the very next rising clock edge, the output of the counter changes to binary 1100 upon which the output of gate x goes low to generate the ld pulse. the ld signal is connected to both the dacs ld and the counters load pins to prevent the thirteenth rising clock edge from advancing the dacs internal shift register. this prevents false loading of data into the dac8512. inverting the dacs serial clock allows sufficient time from the clk edge to the ld edge, and from the ld edge to the next clock pulse all of which satisfies the timing requirements for loading the dac8512. after loading one address of the dac, the entire process can re- peated to load another address. if the loading is complete, then the clock must stop after the thirteenth pulse of the final load. the dacs clock input will be pulled high and the counter reset to zero. as was shown in figure 35, both the 74hc161s and the dac8512s clr pins are connected to a simple r-c timing circuit that resets both ics when the power in turned on. the circuits time constant should be set longer than the power sup- ply turn-on time and, in this circuit, is set to 10 ms, which should be adequate for most systems. this same two-wire inter- face can be used for other three-wire serial input dacs. decoding multiple dac8512s the cs function of the dac8512 can be used in applications to decode a number of dacs. in this application, all dacs re- ceive the same input data; however, only one of the dacs cs input is asserted to transfer its serial input register contents into the destination dac register. in this circuit, shown in figure 37, the cs timing is generated by a 74hc139 decoder and should follow the dac8512s standard timing requirements. to pre- vent timing errors, the 74hc139 should not be activated by its v out3 dac8512 #3 v out2 dac8512 #2 v out1 dac8512 #1 8 4 5 2 3 6 v cc 1g 1a 1b 2g 2a 2b gnd 1y0 1y1 1y2 1y3 2y0 2y1 2y2 2y3 12 1k w +5v 16 1 2 3 15 14 13 8 11 10 9 7 6 5 4 nc nc nc nc +5v enable coded address c1 0.1 m f 74hc139 v out4 dac8512 #4 +5v r1 1k sclk sdi ld 8 4 5 2 3 6 8 4 5 2 3 6 8 4 5 2 3 6 figure 37. decoding multiple dac8512s using the cs pin enable input while the coded address inputs are changing. a simple timing circuit, r1 and c1, connected to the dacs clr pins resets all dac outputs to zero during power-up.
dac8512 C15C rev. a a digitally controlled, ultralow noise vca the circuit in figure 38 illustrates how the dac8512 can be used to control an ultralow noise vca, using the ad600/ ad602. the ad600/ad602 is a dual, low noise, wideband, variable gain amplifier based on the x-amp topology.* both channels of the ad600 are wired in parallel to achieve a wideband vca which exhibits an rti (referred to input) noise voltage spectral density of approximately 1 nv/ ? hz . the output of the vca requires an ad844 configured in a gain of 4 to account for signal loss due to input and output 50 w termina- tions. as configured, the total gain in the circuit is 40 db. since the output of the dac8512 is single quadrant, it was nec- essary to offset the ad600s gain control voltage so that the gain of the circuit is 0 db for zero scale and 40 db at full scale. this was achieved by setting c1lo and c2lo to +625 mv using r1 and r2. next, the output of the dac8512 was scaled so that the gain of the ad600 equaled 20 db when the digital input code equaled 800 h . the frequency response of the vca as a function of digital code is shown in figure 39. *for more details regarding the ad600 or ad602, please consult the ad600/ ad602 data sheet. +70 +20 ?0 100k 100m 10m 1m 10k +30 +40 +50 +60 ?0 ?0 0 +10 frequency ?hz system gain ?db 4095 3072 2048 1024 0 figure 39. vca frequency response vs. digital code 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ref ad600jn v+ v 0.1 m f 0.1 m f 6 2 dac8512fz 8 7 cs clr 1 0.1 m f v+ 1 m f r6 2.26k w r7 1k w 0 v g 1.25v 5 ld 3 sclk 4 sdi r1 619 w r2 4.32k w v+ +625mv 6 3 2 0.1 m f 0.1 m f v+ v out 0.01db/bit 10 m f +5v 10 m f ?v v+ v fb = fair rite #2743001111 supply decoupling network v r5 806 w r3 402 w r4 402 w r4 49.9 w v in ad844 figure 38. a digitally controlled, ultralow noise vca
dac8512 C16C rev. a a serial dac, audio volume control the dac8512 is well suited to control digitally the gain or at- tenuation of a voltage controlled amplifier. in professional audio mixing consoles, music synthesizers, and other audio processors, vcas, such as the ssm2018, adjust audio channel gain and at- tenuation from front panel potentiometers. the vca provides a clean gain transition control of the audio level when the slew rate of the analog input control voltage, v c , is properly chosen. the circuit in figure 40 illustrates a volume control application using the dac8512 to control the attenuation of the ssm2018. 6 2 dac8512 8 +15v 7 cs clr 1 0.1 m f 4 ref02 6 2 18k w 10pf 470k w p1 100k w 10m w offset trim 47pf symmetry trim p2 500k w v out +15v ?5v 30k w +15v ?5v 0.1 m f 0.1 m f +15v 18k w v in 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ssm2018 +5v 0.1 m f c con 1 m f r6 825 w r7 1k w * 0v v c +2.24v * ?precision resistor pt146 1k w compensator 5 ld 3 sclk 4 sdi figure 40. a serial dac, audio volume control since the supply voltage available in these systems is typically 15 v or 18 v, a ref02 is used to supply the +5 v required to power the dac. no trimming of the reference is required be- cause of the references tight initial tolerance and low supply current consumption of the dac8512. the ssm2018 is config- ured as a unity-gain buffer when its control voltage equals 0 volt. this corresponds to a 000 h code from the dac8512. since the ssm2018 exhibits a gain constant of C28 mv/db (typical), the dacs full-scale output voltage has to be scaled down by r6 and r7 to provide 80 db of attenuation when the table iv. ssm-2018 vca attenuation vs. dac8512 input code hexadecimal number control vca in dac register voltage (v) attenuation (db) 000 0 0 400 +0.56 20 800 +1.12 40 c00 +1.68 60 fff +2.24 80 digital code equals fff h . therefore, every dac lsb corre- sponds to 0.02 db of attenuation. table iv illustrates the at- tenuation vs. digital code of the volume control circuit. to compensate for the ssm2018s gain constant temperature coefficient of C3300 ppm/ c, a 1 k w , temperature-sensitive re- sistor (r7) manufactured by the precision resistor company with a temperature coefficient of +3500 ppm/ c is used. a c con of 1 m f provides a control transition time of 1 ms which yields a click-free change in the audio channel attenuation. sym- metry and offset trimming details of the vca can be found in the ssm2018 data sheet. information regarding the pt146 1 k w compensator can be obtained by contacting: precision resistor company, incorporated 10601 75th street north largo, fl 34647 (813) 541-5771 an isolated, programmable, 4-20 ma process controller in many process control system, applications, two-wire current transmitters are used to transmit analog signals through noisy environments. these current transmitters use a zero-scale sig- nal current of 4 ma that can be used to power the transmitters signal conditioning circuitry. the full-scale output signal in these transmitters is 20 ma. the converse approach to process control can also be used; a low-power, programmable current source can be used to control remotely located sensors or de- vices in the loop. a circuit that performs this function is illustrated in figure 41. using the dac8512 as the controller, the circuit provides a programmable output current of 4 ma to 20 ma, proportional to the dacs digital code. biasing for the controller is provided by the ref02 and requires no external trim for two reasons: (1) the ref02s tight initial output voltage tolerance and (2) the low supply current consumption of both the op90 and the dac8512. the entire circuit, including opto-couplers, con- sumes less than 3 ma from the total budget of 4 ma. the op90 regulates the output current to satisfy the current summation at the noninverting node of the op-90. the kcl equation at pin 3 is given by: i out = 1 r 7 1 mv digital code r 3 r 1 + v ref r 3 r 2 ? ? ? ?
dac8512 C17C rev. a clr ld sclk sci dac8512 1 7 8 6 5 3 4 r1 200k w p1 10k w 20ma adjust r3 80.6k d1 r2 976k w p2 50 w 4ma adjust r4 54.9k r5 100k r6 150 w q1 2n1711 ref02 6 2 4 4?0ma op90 3 2 7 6 4 r7 100 w ilq-1 clk sclk +5v 10k w 360 w repeat for sdi, ld, & clr d1 = hp5082-2810 r l 100 w v loop +12 to +40v figure 41. an isolated, programmable, 4-20 ma process controller for the values shown in figure 41, i out = 3.9 m a digital code + 4 ma giving a full-scale output current of 20 ma when the dac8512s digital code equals fff h . offset trim at 4 ma is provided by p2, and p1 provides the circuits gain trim at 20 ma. these two trims do not interact because the noninverting input of the op90 is at virtual ground. the schottky diode, d1, is re- quired in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the op90 more than 300 mv below its inverting input. without this diode, such tran- sients could cause phase reversal of the op90 and possible latchup of the controller. the loop supply voltage compliance of the circuit is limited by the maximum applied input voltage to the ref02 and is from +12 v to +40 v. microprocessor interfacing dac8512Cmc68hc11 interface the circuit illustrated in figure 42 shows a serial interface be- tween the dac8512 and the mc68hc11 8-bit microcontrol- ler. sck of the 68hc11 drives sclk of the dac8512, while the mosi output drives the serial data line, sdi, of the dac8512. the dacs clr , ld , and cs signals are derived from port lines pc1, pd5, and pc0, respectively, as shown. for correct operation of the serial interface, the 68hc11 should be configured such that its cpol bit is set to 1 and its cpha bit is also set to 1. when the serial data is to be transmitted to the dac, pc0 is taken low, asserting the dacs cs input. when the 68hc11 is configured in this manner, serial data on pc1 pc0 sck mosi ss clk sdi ld mc68hc11* dac8512* cs clr *additional pins omitted for clarity figure 42. dac8512Cmc68hc11 interface mosi is valid on the rising edge of sclk. the 68hc11 trans- mits its serial data in 8-bit bytes (msb first), with only eight ris- ing clock edges occurring in the transmit cycle. to load data to the dac8512s input serial register, pc0 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the dac8512. during the second byte load, the first four most significant bits of the first byte are pushed out of the dacs input shift register. at the end of the second byte load, pc0 is then taken high. to prevent an acci- dental advancing of the internal shift register, sclk must al- ready be asserted before pc0 is taken high. to transfer the contents of the input shift register to the dac register, pd5 is taken low, asserting the dacs ld input. the dacs clr in- put, controlled by the 68hc11s pc1 port, provides an asyn- chronous clear function, setting the dac output to zero. included in this section is the source code for operating the dac8512m68hc11 interface.
dac8512 C18C rev. a dac8512Cm68hc11 interface program source code * portc equ $1003 port c control register * 0,0,0,0;0,0,clr/,cs/ ddrc equ $1007 port c data direction portd equ $1008 port d data register * 0,0,ld/,sclk;sdi,0,0,0 ddrd equ $1009 port d data direction spcr equ $1028 spi control register * spie,spe,dwom,mstr;cpol,cpha,sprl,spr0 spsr equ $1029 spi status register * spif,wcol,0,modf;0,0,0,0 spdr equ $102a spi data register; read-buffer; write-shifter * * sdi ram variables: sdi1 is encoded from 0 (hex) to f (hex) * sdi2 is encoded from 00 (hex) to ff (hex) * dac requires two 8-bit loads; upper 4 bits of sdi1 * are ignored. * sdi1 equ $00 sdi packed byte 1 0,0,0,0;msb,db10,db9,db8 sdi2 equ $01 sdi packed byte 2 db7,db6,db5,db4;db3,db2,db1,db0 * org $c000 start of users ram in evb init lds #$cfff top of c page ram * ldaa #$03 0,0,0,0;0,0,1,1 * clr/-hi, cs/-hi staa portc initialize port c outputs ldaa #$03 0,0,0,0;0,0,1,1 staa ddrc clr/ and cs/ are now enabled as outputs * ldaa #$30 0,0,1,1;0,0,0,0 * ldi-hi,sclk-hi,sdi-lo staa portd initialize port d outputs ldaa #$38 0,0,1,1;1,0,0,0 staa ddrd ld/,sclk, and sdi are now enabled as outputs * ldaa #$5f staa spcr spi is master,cpha=1,cpol=1,clk rate=e/32 * bsr update xfer 2 8-bit words to dac8512 jmp $e000 restart buffalo * update pshx save registers x, y, and a pshy psha * ldaa #$0a 0,0,0,0;1,0,1,0 staa sdi1 sdi1 is set to 0a (hex) * ldaa #$aa 1,0,1,0;1,0,1,0 staa sdi2 sdi2 is set to aa (hex) * ldx #sdi1 stack pointer at 1st byte to send via sdi ldy #$1000 stack pointer at on-chip registers * bclr portc,y $02 assert clr/ bset portc,y $02 de-assert clr/ * bclr portc,y $01 assert cs/ *
dac8512 C19C rev. a tfrlp ldaa 0,x get a byte to transfer via spi staa spdr write sdi data reg to start xfer * wait ldaa spsr loop to wait for spif bpl wait spif is the msb of spsr * (when spif is set, spsr is negated) inx increment counter to next byte for xfer cpx #sdi2+1 are we done yet ? bne tfrlp if not, xfer the second byte * *update dac output with contents of dac register * bclr portd,y $20 assert ld/ bset portd,y $20 latch dac register * bset portc,y $01 de-assert cs/ pula when done, restore registers x, y & a puly pulx rts ** return to main program **
dac8512 C20C rev. a outline dimensions dimensions shown in inches and (mm). c1734CxxC11/96 printed in u.s.a. 8-pin plastic dip (p suffix) 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) 0.070 (1.77) 0.045 (1.15) 0.022 (0.558) 0.014 (0.356) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) min 0.210 (5.33) max 0.015 (0.381) typ 4 5 8 1 0 - 15 0.100 (2.54) bsc seating plane 8-pin cerdip (z suffix) 0.005 (0.13) min 0.055 (1.4) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) max 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 0.060 (1.52) 0.015 (0.38) 0 -15 0.100 (2.54) bsc seating plane 4 1 5 8 0.310 (7.87) 0.220 (5.59) 8-lead soic (s suffix) seating plane see detail above 4 5 8 1 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0075 (0.19) 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.1968 (5.00) 0.1890 (4.80) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0040 (0.10) 45 0.0196 (0.50) 0.0099 (0.25) 0.0500 (1.27) 0.0160 (0.41) pin 1 0 - 8

▲Up To Search▲

Price & Availability of DAC8512FS

	To Download DAC8512FS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .